1. Field of the Invention
This invention relates to a static timing analyzer that can suitably be used for computer aided design (CAD) apparatus for LSI devices in order to search for the critical path of a circuit that requires the longest time to pass therethrough by using data on transistors connections. It also relates to a method of static timing analysis that can be used for such an analyzer.
2. Description of the Related Art
Recently, the number of transistors that can be contained in a single LSI unit has been remarkably increasing and more and more complex circuits are currently being used for microprocessors and other system devices. Thus, the use of CAD apparatus is indispensable for the manufacture of semiconductor devices if large scale and complex semiconductor devices of high performance are to be designed without requiring a long design phase. Static timing analysis systems have been proposed as a useful tool to be used for CAD apparatus in order to search for the critical path of a circuit on the basis of data on transistor connections. The static timing analysis system has been increasingly getting popularity in recent years because it does not require the use of a combinational sequence of input signals referred to as a test vector and hence involves only a short run time. Known static timing analysis systems include those that carry out analytic operations at gate level of inverter circuits and NAND-circuits and those that execute analytic operations at transistor level. As for the algorithm for searching for paths, different algorithms have been known that include the one named as Path Mill and marketed by EPIC.
Additionally, a technique named as Gated Clock has recently been developed for designing power saving microprocessors. It is a technique of gating clock signals by means of NAND-circuits and other circuits that requires a static timing analysis to be conducted on the designed circuit.
Meanwhile, a number of algorithms have been proposed for static timing analysis systems that read and analyze net lists at transistor level.
FIG. 10 of the accompanying drawings illustrates, as an example, a known method of static timing analysis. The processing flow of FIG. 10 proceeds in a manner as described below. Firstly, a net list is read out of a memory and then stretched out to construct a data structure from it (Step S11). Thereafter, the starting point and the terminating point of each path searching operation that have been designated by the user by means of an editor are recognized from the generated data structure (Step S12). A synchronous sequential circuit (hereinafter referred to simply as sequential circuit) is identified and divided into combinational circuits on the basis of the starting point and the terminating point of each path searching operation (Step S13). All the combinational circuits obtained by the division are subjected to path searching operations for static timing analysis (Steps S14, S15) and the obtained results are produced as output (Step S16).
The method of FIG. 10, however, is cumbersome in that the user has to designate starting and terminating points for all path searching operations. This by turn reduces the efficiency of design work and prolongs the time required for it.
FIG. 11 illustrates another known method of static timing analysis. With this method, firstly, a net list is read out of a memory and then a data structure is constructed from it (Step S21). Thereafter, a pattern matching operation is carried out by using a set of predetermined rules and user-defined rules to convert the nets that are expressed at transistor level into those expressed at gate level (Step S22). Then, a sequential circuit is identified and divided into combinational circuits (Step S13). All the combinational circuits obtained by the division are subjected to path searching operations at gate level for static timing analysis (Steps S24, S25) and the obtained results are produced as output (Step S26).
The known method of FIG. 11 is very time-consuming because of the pattern matching operation. Additionally, it is cumbersome to the user because the he or she is required to define rules for pattern matching. Generally speaking, a higher timing accuracy can be achieved at transistor level than at gate level in the path searching operation and, therefore, the searched paths can be accurately verified for activation to reduce the number of false paths. However, since the path searching operation is conducted at gate level with the method of FIG. 11, it is accompanied by a poor timing accuracy and hence cannot reduce the number of false paths to consequently reduce the efficiency of design work and prolong the time required for it.
FIG. 12 illustrates still another known method of static timing analysis. With this method, firstly, a net list is read out of a memory and then a data structure is constructed from it (Step S31). Thereafter, the signal input and output terminals and the clock node for receiving clock signals that have been defined by the user are recognized (Step S32). The starting point and the terminating point of each path searching operation are designated on the basis of the recognized clock node (Step S33). The above described Path Mill marketed by EPIC may be used for designating the starting and terminating points of each path searching operation. It is a system that sequentially verify all the nodes starting from the clock node specified by the user. If the search operation finally gets to the gate of a transistor other than the inverter circuit, the node is defined as the terminating point of the path searching operation while the source or drain of the transistor is designated as the starting point of the path searching operation. After defining the starting and starting points for all the path searching operations, the operations are actually carried out from the respective starting points down to the respective terminating points (Step S34, S35). When all the path searching operations are over, the obtained results are produced as output (Step S36).
The known method of FIG. 12 is better than that of FIG. 11 in terms of timing accuracy because the path searching operations are carried out at transistor level with it. However, when the starting and terminating points are designated for path searching operations, paths are searched for only if the clock signal is at a high level and not if at a low level and, therefore, it is difficult to discriminate between precharge circuits and latch circuits with this method. Additionally, since the output of a NAND-circuit is not recognized as clock with this method, it cannot adapt itself to the clock gate that is currently being popularly used as a tool for designing LSI devices. Still additionally, the sequential circuit is not divided into combinational circuits with this method. Therefore, it is not verified if each searched path can be activated or not and there can be given rise to a large number false paths to consequently reduce the efficiency of design work and prolong the time required for it.
As discussed above, any known path analysis systems cannot identify the sequential circuit and can give rise to a large number of false paths because paths are not satisfactorily searched for at the time of designating starting and terminating points for path searching operations. Furthermore, such known path analysis systems are burdensome to the user and cannot analyze circuits designed by using the gated clock technique so that they entail a low efficiency and a long work time for design works.